1. Field of the Invention
The present invention relates to memory devices and systems including error correction code logic.
2. Description of Related Art
Memory technologies used for integrated circuit memories are being developed at smaller and smaller technology nodes, and are being deployed on larger and larger memory arrays on a single integrated circuit. As the technology for memory cells advances, the margins for sensing the data can become tighter. Also, the ability of the memory cells to hold data values in the presence of disturbance of the memory cell state caused by high speed and high volume accesses to the memory cells and to neighboring memory cells can be limited by the tighter margins.
To address issues like those that arise from tighter margins and memory cell disturbance, as these technologies scale in size and density, use of error correcting codes (ECC) embedded with integrated circuit memory has become more widespread. Hamming codes are one known type of ECC, and in common forms can provide for single bit error correction and detection of two bit errors in the protected data. Single bit correction may not be sufficient for some memory technologies. In this case, multibit ECC technologies such as BCH codes can be applied. However, utilizing BCH codes can involve significant hardware overhead, and remains limited in the scope of error correction possible.
It is desirable to improve the performance of ECC technologies, while limiting the hardware overhead needed on integrated circuits in which such technologies are applied.